The present invention relates to a synchronous semiconductor memory based on the double data rate (to be referred to as DDR hereinafter) scheme, which is used for, for example, a static RAM.
A general synchronous semiconductor device is read or written in synchronism with the up-edge of an operation clock. In this specification, a synchronous semiconductor memory of this type will be referred to as a single data rate (SDR) scheme memory. A synchronous semiconductor memory based on the SDR scheme is read or written once per operation clock cycle.
Aside from such SDR scheme, a synchronous semiconductor memory based on the DDR scheme has recently received attention.
A synchronous semiconductor memory based on the DDR scheme is read or written in synchronism with both the up-edge and down-edge of an operation clock instead of its up-edge alone. That is, data is read or written twice per operation clock cycle. This can increase the data transfer rate to twice that of the SDR scheme, and is advantageous for an increase in data transfer amount per unit time.
Attempts have also been made to develop a memory in which both the DDR scheme and the SDR scheme are implemented on one chip, and one of the schemes can be selected in accordance with a command signal. A memory of this type is read/written by the DDR scheme when the DDR scheme is ordered, and is read/written by the SDR scheme when the SDR scheme is ordered.
FIG. 1 is a block diagram showing a synchronous SRAM that can select either the DDR scheme or the SDR scheme.
As shown in FIG. 1, an address ADD is input to an address register 101. The address register 101 outputs the input address ADD in synchronism with the up-edge of an operation clock CK. The address ADD outputted from the address register 101 are input to an SRAM core 102. One of the memory cells (not shown) included in the SRAM core 102 which corresponds to the input address signals ADD are connected to data line BUS0 or BUS1 (SDR scheme). In the DDR scheme, two memory cells are designated by the single address ADD. One of the two designated memory cells is connected to one of the data line BUS0, and the other memory cell is connected to the data line BUS1. This specification is based on the premise that a least significant bit A0 of the address ADD determines whether to connect the corresponding memory cell to the data line BUS0 or BUS1. This applies to both the SDR scheme and the DDR scheme. A data output circuit 103 and a data input circuit 104 are connected to the data lines BUS0 and BUS1.
[Data Output Circuit 103]
The data output circuit 103 includes output registers 105-0 and 105-1 and transfer gates 106-0 and 106-1.
The output register 105-0 is connected to the data line BUS0. The output register 105-1 is connected to the data line BUS1. The output register 105-0 stores the data read out to the data line BUS0. The output register 105-1 stores the data read out to the data line BUS1. Each of the output registers 105-0 and 105-1 outputs the stored data in synchronism with the up-edge of the operation clock CK.
The output transfer gate 106-0 is connected to the output register 105-0. The output transfer gate 106-1 is connected to the output register 105-1. The output transfer gate 106-0 outputs the data stored in the output register 105-0 while an output control clock CK1 stays at "H" level. The output transfer gate 106-1 outputs the data stored in the output register 105-1 while an output control clock CK2 stays at "H" level. The output control clock CK2 is a clock that is opposite in phase to the output control clock CK1. These output control clocks CK1 and CK2 are generated by an output control clock generating circuit 107. FIG. 2 shows the output control clocks generated by the output control clock generating circuit 107.
The output control clock generating circuit 107 generates the output control clocks CK1 and CK2 from the operation clock CK and an inverted operation clock /CK that is opposite in phase to the operation clock CK. The output control clock generating circuit 107 includes a frequency-dividing circuit 108, a multiplexer 109, and a clock generating circuit 110. The frequency-dividing circuit 108 doubles the period of the operation clock CK to generate operation clocks 2.multidot.CK and 2.multidot./CK each having a period twice that of the operation clock CK. The multiplexer 109 selects either the operation clocks CK and /CK or the operation clocks 2.multidot.CK and 2.multidot./CK in accordance with an internal command signal Double/Single. The internal command signal Double/Single is a signal for ordering the DDR or SDR scheme. When the DDR scheme is ordered, the multiplexer 109 selects the operation clocks CK and /CK and supplies them to the clock generating circuit 110. When the SDR scheme is ordered, the multiplexer 109 selects operation clocks 2.multidot.CK and 2.multidot./CK and supplies them to the clock generating circuit 110. The clock generating circuit 110 generates the output control clocks CK1 and CK2 in accordance with the least significant bit A0 of the address ADD, as shown in FIG. 2. The least significant bit A0 of the address ADD determines whether the memory cell corresponding to the input address is connected to the data line BUS0 or BUS1.
In this manner, the transfer gates 106-0 and 106-1 are switched/controlled by the output control clocks CK1 and CK2 in accordance with the input address ADD.
[Data Input Circuit 104]
The data input circuit 104 includes input registers 111-0, 111-1, 112-0, and 112-1.
The input register 111-0 outputs the data stored therein while an input control clock CK3 stays at "H" level. The input register 111-1 outputs the data stored therein while an input control clock CK4 stays at "H" level. These input control clocks CK3 and CK4 are generated by an input control clock generating circuit 113. FIG. 3 shows the input control clocks generated by the input control clock generating circuit 113.
The input control clock generating circuit 113 generates the input control clocks CK3 and CK4 from the operation clock CK and the inverted operation clock /CK that is opposite in phase to the operation clock CK. The input control clock generating circuit 113 includes timing adjusting circuits 114 and 115 and a multiplexer 116. The timing adjusting circuit 114 generates a clock CK' that is synchronous with the up-edge of the operation clock CK and has a pulse width shorter than that of the operation clock CK. The timing adjusting circuit 115 generates a clock /CK' that is synchronous with the up-edge of the inverted operation clock /CK and has a pulse width shorter than that of the inverted operation clock /CK. The multiplexer 116 selects the clock CK' or /CK' in accordance with the internal command signal Double/Single and the least significant bit A0 of the address ADD. When the SDR scheme is ordered, the multiplexer 116 selects the clock CK' as the input control clocks CK3 and CK4 regardless of the least significant bit A0 of the address ADD. When the DDR scheme is ordered, the multiplexer 116 selects the clock CK' as one of the input control clocks CK3 and CK4 and also selects the clock /CK as the other of the input control clocks CK3 and CK4 in accordance with the least significant bit A0 of the address ADD.
The input register 112-0 stores an output from the input register 111-0. The input register 112-1 stores an output from the input register 111-1. The input register 112-0 is connected to the data line BUS0. The input register 112-1 is connected to the data line BUS1. Each of the input registers 112-0 and 112-1 outputs the stored data in synchronism with the up-edge of the operation clock CK.
In this way, the input registers 111-0 and 111-1 are switched/controlled by the input control clocks CK3 and CK4 in accordance with the input address ADD.
A burst address counter 117 in FIG. 1 generates a burst address when burst operation is ordered. The burst address counter 117 is activated when an internal command signal Burst is activated. The internal command signal Burst is a signal for ordering burst operation. The burst address counter 117 consecutively converts one address ADD into four burst addresses by incrementing, for example, the two lower bits of the address ADD outputted from the address register 101.
In the above synchronous SRAM, the transfer gates 106-0 and 106-1 and the input registers 111-0 and 111-1 are respectively controlled by the output control clocks CK1 and CK2 and the input control clocks CK3 and CK4, which are generated from the operation clocks CK and /CK. With this control, either the DDR scheme or the SDR scheme can be selected.
Since the clocks CK1, CK2, CK3, and CK4 are generated from the operation clocks CK and /CK, the clocks CK1, CK2, CK3, and CK4 are delayed from the operation clocks CK and /CK. For example, the output control clocks CK1 and CK2 are delayed by a delay time Td1 produced via the output control clock generating circuit 107. For this reason, the output timing of the data is delayed by a delay time Td1 behind the operation clocks CK and /CK.
As shown in FIG. 4, when, after the outputting of the data A4 (least significant bit A0=1), the data B1 (least significant bit A0=1) is subsequently output, the output control clock CK2 is maintained at the "H" level. In this case, the output timing of the data B1 is not delayed by the delay time Td1 behind the operation clocks CK, /CK. And the output time of the data A4 will be shortened to an extent to which the output timing of the data B1 is not delayed.
The input control clocks CK3, CK4 are delayed by a delay time Td2 produced via the input control clock generating circuit 113.
For this reason, as shown in FIG. 5, the outputs timing of the input registers 111-0 and 111-1 are delayed by a delay time Td2 behind the operation clocks CK, /CK.
As shown in FIG. 5, when, after the inputting of the data A4 (least significant bit A0=1), the data B1 (least significant bit A0=1) is subsequently input, it is necessary to set the input control clock CK4 from a "L" level to a "H" level, two times, in one cycle. For this reason, the time at which the input register 111-1 outputs the data A4 will be shortened.
In the case where the frequencies of the operation clocks CK, /CK are raised in order to improve the operation speed, it becomes difficult to adequately obtain the output time of the data at a read operation time or the output time of the input register 111-0 or 111-1 at a read operation time.